1. Field of the Invention
This invention relates to integrated circuits and particularly to the family of logic circuits.
2. Description of the Related Art
Tying off unused logic inputs to the supply rails (Vcc and GND) can be risky due to the damaging consequences of electrostatic discharge (ESD), particularly where the inputs are tied to transistor gates. FIGS. 1a and 1b show the schematic and block diagram, respectively, for a conventional tie-off circuit. This type circuit has been used to provide logic high (HI) and logic low LO) voltages that reduce the ESD risk when tying off unused inputs. As shown in the block diagram 7 of FIG. 1b, the circuit consists logically of a two-input NAND gate 9 and an inverter 8 with the NAND gate""s 9 output tied to one of it""s inputs (I1) and to the inverter""s 8 input. The output of the inverter 8 is tied to the second input (I2) of the NAND gate 9. The HI tie-off voltage is taken from the output of the NAND gate 9 and the LO tie-off voltage is taken from the output of the inverter 8. Since the inverter 8 assures that one of the NAND gate""s inputs is complementary to it""s other input, under normal conditions one input to the NAND gate 9 will always be a logic LO level, forcing the NAND gate""s output to a logic HI level and as a result the output of the inverter will always be at a logic LO level.
In the schematic for the conventional tie-off circuit of FIG. 1a, the inverter 8 consists of a p-channel transistor 5 and an n-channnel transistor 6 pair. The gates of these two transistors 5,6 are tied together to form the inverter""s input and the drains of the transistors 5,6 are also tied together to form the inverter""s output at node 2 (N2). To complete the inverter circuit, the source of the p-channel transistor 5 is tied to Vcc and the source of the n-channel transistor 6 is tied to GND. The NAND gate 9 consists of two p-channel input transistors 1,2 and two n-channel transistors 3,4. The gates of one of the p-channel transistors 1 and one of the n-channel transistors 3 are tied together to form input I2 of the NAND gate 9, which is connected to the output of the inverter 8 at node 2 and to the LO output terminal of the circuit. The drains of these two transistors 1,3 are tied together to form the HI output terminal at node 1 (N1) and also connects to the I1 input of the NAND gate 9 and to the input of the inverter 8. The sources of the two p-channel transistors 1,2 are tied to Vcc. In the NAND gate circuit, the two n-channel transistors 3,4 are connected in series with the source of one of these transistors 3 connected to the drain of the other transistor 4. Finally, the source of transistor 4 is connected to GND. In this circuit configuration, one of the two n-channel transistors 3,4 is always OFF so that no current flows through this portion of the circuit.
The above degenerative (negative feedback) circuit consists of n-channel, p-channel transistor pairs that can under certain conditions, converge with HI and/or LO outputs in an alternative state where the HI and LO output levels are at voltages intermediate between VDD and GND. In other words, the HI and LO levels are not uniquely defined and for certain conditions a metastable state can exist with poorly defined HI and/or LO levels. Such things as process spread, supply resistance, and GND resistance can cause these uncertain conditions. FIG. 2 illustrates the possible metastable states that can exist where the HI output is less than the logic 1 level and/or the LO output is greater than the logic 0 level; e.g., given as:
HI=xcex1 Vcc, where 0 less than xcex1 less than 1 , and
LO=xcex2 Vcc, where 0 less than xcex2 less than 1.
The metastable level characteristics for the NAND gate and inverter, respectively, are as follows:
xcex1=ƒ(xcex1,xcex2) and
xcex2=ƒ(xcex1).
As a result, it is possible that xcex1 can be significantly low and/or that xcex2 can be significantly high so that incorrectly defined logical levels result. This means that it is possible to have tie-off levels where the HI and LO levels are significantly below the Vcc and/or above the GND level to the extent that it effects the logical output of the overall circuit function.
There is a recognized need for a tie-off circuit which provides for ESD protection and at the same time has uniquely defined HI and LO output levels that correspond to the Vcc and GND levels, respectively. The invention described herein addressed this need.
A regenerative tie-high, tie-low cell (circuit) for tying off logic inputs that provides unconditionally stable logic 1 and 0 output states, is disclosed. The circuit provides uniquely defined HI and LO states to overcome the poorly defined metastable states that can exist in conventional circuits of this type, where the circuit can converge with HI and/or LO outputs in an alternative state with intermediate HI and LO output voltage levels between VDD and GND. The circuit eliminates p-channel/n-channel transistor pair current paths and adds a regenerative transistor to force the circuit to its desired operating state.
Finally, in a first preferred embodiment, the circuit consists of only three CMOS transistors, reducing the required silicon area and in turn improving the reliability and lowering the cost of fabricated ICs.